A phase noise characteristic of a signal generated in a PLL (Phase-Locked Loop) circuit is used as an indicator that represents purity of the signal. Phase noise of a PLL circuit is an important performance indicator because the phase noise is a characteristic that influences performance of a wireless device.
A PLL circuit includes, in general, a phase comparator, a loop filter, a VCO (voltage-controlled oscillator), and a divider. The divider divides an oscillation signal output from the VCO by N to generate a divided signal. The phase comparator compares a phase of a reference signal from a reference oscillator with a phase of the divided signal, and outputs a signal that indicates a phase comparison result. The loop filter calculates an integral of the signal that indicates the phase comparison result, and supplies a voltage signal to the VCO at a voltage level that depends on the integral result. The VCO oscillates at a frequency depending on the voltage signal. While the VCO oscillates depending on the voltage signal generated by the loop filter, if a frequency difference between the reference signal and the divided signal is zero, the voltage signal converges to a certain voltage, and the PLL circuit transitions to a locked state.
FIG. 1 is a schematic view illustrating a typical phase noise characteristic in a PLL circuit. The horizontal axis represents frequency, and the vertical axis represents phase noise power. f0 is an oscillation frequency of the PLL circuit. Phase noise of the PLL can be classified into phase noise in region 10, phase noise in region 11, and phase noise in region 12. In the phase noise in region 10, phase noise at the reference oscillator is dominant. In the phase noise in region 11, phase noise at the phase comparator is dominant. In the phase noise in region 12, phase noise at the VCO is dominant. Note that the phase noise is generated with major causes such as thermal noise of a resistor, a fluctuation of a current flowing through an active element, and the like.
Among the above phase noise, the phase noise in region 11 has a greater influence on performance of a wireless device. This phase noise in region 11, or SPLL, can be represented by the following formula in theory.SPLL≈SPD/Kd2·N2   (1)
where SPD represents output noise of the phase comparator, Kd represents gain of the phase comparator, and N represents a division ratio of the divider. As above, three major factors determines the phase noise in region 11. It can be understood from the above formula (1) that the phase noise of region 11 can be reduced by making the division ratio N smaller.
In a general PLL circuit, a reference signal and a divided signal are set to the same frequency. In contrast to that, to reduce the phase noise of region 11 by making the division ratio N smaller, there is a technology in which multiple or M phase comparators are arrayed to reduce the division ratio N to 1/M (see, for example, Non-Patent Document 1). In this technology, M reference signals are generated based on a reference signal having a cycle T so that the generated M reference signals have a cycle T and respective time intervals shifted sequentially by T/M. Each of these M phase comparators performs phase comparison between an edge of each of these M reference signals and a corresponding edge of the divided signal having a cycle T/M. As a result, outputs of the multiple M phase comparators are obtained at timings that are shifted sequentially by T/M. Then, by superposing these outputs by a SUM circuit, a phase comparison result is obtained that has a cycle T/M. This makes it possible to generate an oscillation signal having a frequency that is N times greater than the reference signal while the division ratio is set to N/M and the phase noise is reduced by 1/M2 times less.
However, this technology has the following problems: the circuit area and the power consumption of the delay circuit are great; and the circuit area and the power consumption of the SUM circuit are also great.